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d a t a sh eet preliminary speci?cation file under integrated circuits, ic01 may 1994 integrated circuits philips semiconductors saa7366 bitstream conversion adc for digital audio systems
may 1994 2 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 features integrated buffers for simple interfacing to analog inputs 4 flexible serial interface modes overload detection of digital signal 3- 1 db amplitude selectable high-pass filter 18-bit serial output 3.4 to 5.5 v operation of digital part standby mode so24 package small non-critical pcb layout. general description the saa7366 is a cmos cost effective stereo analog-to-digital converter (adc) using the philips bitstream conversion technique. applications the device is designed for digital acquisition of analog audio signals for digital audio systems such as: cd-recordable digital compact cassette (dcc) digital audio tape (dat). quick reference data ordering information note 1. plastic small outline package; 24 leads; body width 7.5 mm; (sot137a); sot137-1; 1996 oct 29. symbol parameter min. typ. max. unit v ddd digital supply voltage 3.4 5.0 5.5 v v dda analog supply voltage 4.5 5.0 5.5 v f i clock input frequency 4.608 12.288 13.568 mhz thd + n total harmonic distortion + noise --- 80 db dr dynamic range 90 -- db type number package pins pin position material code SAA7366T (1) 24 so24l plastic sot137a
may 1994 3 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 block diagram fig.1 block diagram. mga911 saa7366 operational amplifier reference voltage generator clock generation and control sigma- delta modulator reference current generator timing generator decimation filter stage 1 comb filter stage 2 3 half-band filters high-pass filter serial output interface w 3 k 1 pf w 10 k w 3 k w 10 k sigma- delta modulator reference voltage generator w 3 k 1 pf w 10 k w 3 k w 10 k operational amplifier operational amplifier operational amplifier 16 17 18 14 19 20 21 22 23 11 24 1 9 8 7 3 5 6 4 2 10 12 15 13 sfor std ovld ckin v ddd v ssd sdo sws sck test1 hpen test2 slave v dda v refl bil bol v dacp v dacn bor bir v refr i ref v ssa
may 1994 4 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 pinning symbol pin description sfor 1 serial interface output format select. output format is selected as follows: sfor high = format 1; sfor low = format 2. std 2 standby mode input (active low). ovld 3 overload indication output. this pin indicates whether the internal digital signal is within 1 db of maximum. in standby mode this output is high impedance. ckin 4 system clock input. v ddd 5 supply for the digital section (3.4 to 5.5 v). v ssd 6 ground supply for the digital section. sdo 7 serial interface data output. in standby mode this output is high impedance. sws 8 serial interface word select signal. in master mode this pin outputs the serial interface word select signal. in slave mode this pin is the word select input to the serial interface. in standby mode this pin is always an input (high impedance). sck 9 serial interface clock. in master mode this pin outputs the serial interface bit clock. in slave mode this pin is the input for the external bit clock. in standby mode this output is high impedance. test1 10 test input 1. this pin should be left open-circuit. hpen 11 high-pass ?lter enable input. (hpen high = enabled). if unconnected this pin defaults high. test2 12 test input 2. this pin should be left open-circuit. v ssa 13 ground supply for the analog section. i ref 14 current reference output node. v refr 15 1 2 v dda reference generator output for the right channel analog section. bir 16 buffer operational ampli?er inverting input for right channel. bor 17 buffer operational ampli?er output for right channel. v dacn 18 negative 1-bit dac reference voltage input, connected to 0 v. v dacp 19 positive 1-bit dac reference voltage input, connected to +5 v. bol 20 buffer operational ampli?er output for left channel. bil 21 buffer operational ampli?er inverting input for left channel. v refl 22 1 2 v dda reference generator output for the left channel analog section. v dda 23 supply for the analog section. slave 24 serial interface operating output mode master/slave select as follows: high = slave mode; low = master mode. if unconnected the pin will default low.
may 1994 5 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 functional description general the saa7366 is a bitstream conversion cmos adc for digital audio systems. the conversion is achieved using a third order sigma-delta modulator (sdm), operating at 128 times the output sample frequency (f s ). the high oversampling ratio greatly simplifies the design of the analog input anti-alias filter. in most cases the internal buffer operational amplifier, configured as a low-pass filter will suffice. the 1-bit code from the sigma-delta modulator is filtered and down-sampled (decimated) to 1f s in two stages of filtering. an optional high-pass filter is provided to remove dc, if required. the device has been designed with ease of use, low board area and low application costs in mind. clock frequency the external clock, input on pin ckin, operates at 256 times f s , which can range from 18 khz to 53 khz. input buffer two input buffers are provided, one for each channel, for signal amplitude matching, signal buffering and anti-alias filter purposes. these are configured for inverting use. access is provided by pins bil, bir (inverting inputs) and bol, bor (outputs) for left and right channels fig.2 pin configuration. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 mga912 sfor std ovld ckin v ddd v ssd sdo sws sck test1 hpen test2 slave v dda v refl bil bol v dacp v dacn bor bir v refr i ref v ssa saa7366 respectively. by the choice of feedback component values, the application signal amplitude can be matched to the requirements of the adc. typically the operational amplifiers are configured as low-pass filters with a gain of 1 and a pole at approximately 5f s . remark: the complete adc is non-inverting. hence a positive dc input (referenced to v ref ) will yield a positive digital output. input level the overall system gain is proportional v dda , or more accurately {v(v dacp ) - v(v dacn )}. for convenience the adc input signal amplitude is defined as that amplitude seen on bol or bor, the operational amplifier outputs (i.e. the input to the sigma-delta modulator). also, the 0 db input level is defined as that which provides a - 1db (actually - 1.08 db) digital output, relative to full-scale swing. this offset provides headroom to accommodate small random dc offsets without causing the digital output to clip. hence: the user of the ic should ensure, that when all sources of signal amplitude variation are taken into account, the maximum input signal should conform to the 0 db level. if not, clipping may occur. in the event that the maximum signal level cannot be pre-determined, e.g. a live microphone input, the average signal level should be set at - 10 to - 20 db down. the exact value will depend on the application and the balance between head room and operating signal-to-noise ratio. behaviour during overload as defined earlier the maximum input level for normal operation is 0 db. if the input level exceeds this value clipping may occur. infringements are limited to the maximum permitted positive or negative values, 2 17 - 1 or - 2 17 respectively. if the high-pass filter has been enabled the clipped output samples may have non-maximum values due to the removal of the dc content. input signals in the range of 0 to 1 db may or may not be clipped depending on the values of dc dither and small random offsets in the analog circuitry. when using the recommended application circuitry, clipping will initially be observed on negative peaks due to the use of negative dc dither. the maximum level of overload that can be safely tolerated is application circuit dependent. in the case of the v i 0db () vv dacp () vv dacn () C 5 --------------------------------------------------------------- - v (rms) ==
may 1994 6 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 recommended circuit the following applies: the inverting operational amplifier inputs bil/bir are protected from excessive voltages (currents) by diodes to v dda and v ssa . these have absolute maximum ratings of i ik = 20 ma, with a safe practical limit of 2 ma. given the input resistor of 10 k w , 2 ma diode current and the operation of the operational amplifier a maximum signal (applied to the input resistor) of 30 v can be handled safely. this level represents an overload of 26 db. during overload the in-band portion of the waveform will be correctly converted. the out-of-band portion will be limited as detailed above. sigma-delta modulator the saa7366 has two third order sigma-delta modulators with a quantization noise floor of approximately - 104 db. the scaling of the feedback has been optimized for stable operation even during overload. thus with a maximum signal swing of 0 v to v dda on the input the digital output remains well behaved, i.e. it does not burst into random oscillation. during overload the output is simply a clipped version of the input. the gain of this stage is - 4.95 db. decimation ?lter decimation from 128f s is performed in two stages. the first stage is a comb filter, which decimates from 128 to 8f s . the second stage, consists of 3 half-band filters, each decimating by a factor of 2. the overall characteristics are given in table 1. table 1 overall ?lter characteristics. high-pass ?lter an optional high-pass filter is provided to remove unwanted dc components. the operation is selected when hpen is high. the filter has the characteristics given in table 2. item condition value (db) pass band ripple 0 to 0.45f s hz 0.1 0.45 to 0.47f s - 0.5 stop band > 0.55f s - 60 dynamic range 0 to 0.42f s 110 gain dc 3.87 table 2 high-pass ?lter characteristics. serial interface the serial interface provides 2 formats in both master and slave modes (see figs 3 and 4). in both modes the interface provides up to 18 significant bits of output data per channel. during standby mode ( std = low) all interface pins are in their high-impedance state. on recovery from standby the serial data output sdo is held low until valid data is available from the decimation filter. this time depends on whether the high-pass filter is selected or not as follows: hpen = 0; t = 1024/f s , t = 21.3 ms when f s = 48 khz hpen = 1; t = 8192/f s , t = 170.6 ms when f s = 48 khz overload detection indication (ovld) the ovld output is used to indicate whenever the data, in either the left or right channel, is within 1 db of the maximum possible digital swing. when this condition is detected the ovld output is forced high for at least 512f s cycles (10.6 ms at f s = 48 khz). this time-out is reset for each infringement. standby mode ( std) the std pin activates a power saving mode when the device function is not required. this pin can also be used as a chip enable, as follows. on a high-to-low transition, of the std pin, the internal control circuitry starts a timed power-down sequence. this takes approximately 32 system clock cycles to complete. transitions on std which are shorter than 32 clock cycles have an indeterminate effect. however, the device will always recover correctly. item condition value (db) pass band ripple none pass band gain 0 droop at 0.00045f s 0.029 attenuation at dc at 0.00000036f s > 40 dynamic range 0 to 0.45f s 116
may 1994 7 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 during standby the following occurs: the internal logic clock is disabled the serial interface pins are forced to high impedance the ovld output is forced low the analog circuitry is disabled the nominal external analog node voltages are maintained by a low-power circuit. this feature ensures a fast recovery from standby mode. on a low-to-high transition the device reverts back to its normal function. this process takes approximately 32 system clock cycles. before sdo is enabled the output data is forced low. sdo remains low until good data is available from the decimation filter. the std pin has a schmitt-trigger input. a simple power-on reset function can be effected using an external capacitor to v ssd and resistor to v ddd . limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. v ssd and v ssa pins must be externally connected to a common potential. 2. equivalent to discharging a 100 pf capacitor via a 1.5 k w series resistor with a rise time of 15 ns. 3. equivalent to discharging a 200 pf capacitor via a 2.5 m h series inductor. handling inputs and outputs are protected against electrostatic discharges in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. characteristics v ddd = 3.4 to 5.5 v; v dda = 4.5 to 5.5 v; t amb = - 40 to +85 c; f s = 18 to 53 khz; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dda analog supply voltage note 1 - 0.5 +6.5 v v i dc input voltage - 0.5 +6.5 v i ik dc input diode current - 20 ma v o dc output voltage - 0.5 v dd + 0.5 v i o dc output source or sink current - 20 ma i ddtot total dc supply current - 0.5 a i sstot total dc supply current - 0.5 a t amb operating ambient temperature - 40 +85 c t stg storage temperature - 65 +150 c v es1 electrostatic handling note 2 - 2000 +2000 v v es2 electrostatic handling note 3 - 200 +200 v symbol parameter conditions min. typ. max. unit supply v dda analog supply voltage 4.5 5.0 5.5 v i dda analog supply current f s = 48 khz - 13 - ma v ddd digital supply voltage 3.4 5.0 5.5 v i ddd digital supply current f s = 48 khz - 56 - ma p tot total power consumption f s = 48 khz - 345 - mw
may 1994 8 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 i std standby supply current - 65 -m a p std standby power consumption - 325 -m w digital part: inputs sfor, slave and hpen v il low level input voltage note 1 - 0.5 - +0.8 v v ih high level input voltage note 1 2.0 - v ddd + 0.5 v i li input leakage current note 2 - 10 - +10 m a c i input capacitance -- 10 pf clkin v il low level input voltage - 0.5 - +0.3v ddd v v ih high level input voltage 0.7v ddd - v ddd + 0.5 v i li input leakage current note 2 - 10 - +10 m a c i input capacitance -- 10 pf std (s chmitt-trigger ) v il low level input voltage note 1 - 0.5 - +0.4v ddd v v ih high level input voltage note 1 2.4 - v ddd + 0.5 v d v i input hysteresis - 600 - mv i li input leakage current note 2 - 10 - +10 m a c i input capacitance -- 10 pf digital part: input/outputs sws and sck v il low level input voltage note 1 - 0.5 - +0.8 v v ih high level input voltage note 1 2.0 - v ddd + 0.5 v i li leakage current in 3-state note 2 - 10 - +10 m a c i input capacitance -- 10 pf v ol low level output voltage i o = - 400 m a; note 1 -- 0.4 v v oh high level output voltage i o =20 m a; note 1 2.4 -- v c l output load capacitance -- 50 pf digital part: outputs ovld v ol low level output voltage i o = - 400 m a; note 1 -- 0.4 v v oh high level output voltage i o =20 m a; note 1 2.4 -- v c l output load capacitance -- 50 pf symbol parameter conditions min. typ. max. unit
may 1994 9 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 sdo v ol low level output voltage i o = - 400 m a; note 1 -- 0.4 v v oh high level output voltage i o =20 m a; note 1 2.4 -- v i li leakage current in 3-state note 2 - 10 - +10 m a c l output load capacitance -- 50 pf digital part: timing ckin t r clock input rise time -- 10 ns t f clock input fall time -- 10 ns f i clock input frequency note 3 4.608 12.288 13.568 mhz msr mark-to-space ratio f s > 32 khz 40 - 60 % f s 32 khz 30 - 70 % serial interface master and slave modes (see figs 5, 6 and 7) sck t r clock rise time note 4 -- 50 ns t f clock fall time note 4 -- 50 ns t l clock low time t = 1/64f s 0.40t - 0.60t t h clock high time t = 1/64f s 0.40t - 0.60t f clk clock frequency master mode 64f s 64f s 64f s slave mode -- 64f s t idle burst clock idle time slave mode; t = 1/f s 0 - 0.05t sws t r word select rise time note 4 -- 50 ns t f word select fall time note 4 -- 50 ns t wl word select low time t = 1/f s 0.45t 0.50t 0.55t t wh word select high time t = 1/f s 0.45t 0.50t 0.55t f wc word select frequency 1f s 1f s 1f s t d word select delay from sck master mode - 50 - +50 ns t d word select delay from sck slave mode 50 -- ns t su word select set-up time to sck slave mode 150 -- ns sdo t h data output hold time 100 -- ns t su data output set-up time 100 -- ns t r data output rise time note 4 -- 50 ns t f data output fall time note 4 -- 50 ns symbol parameter conditions min. typ. max. unit
may 1994 10 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 notes 1. minimum v il , v ol and maximum v ih , v oh are peak values to allow for transients. 2. i limin and i lomin measured at v i = 0 v; i limax and i lomax measured at v i =v ddd . 3. f i is a multiple ( 256) of the system sampling frequency (f s ) which can vary between 18 khz and 53 khz. 4. c l = 50 pf (valid for master mode only). 5. device measured with external components shown in recommended application diagram fig.8. 6. input is 1 khz and - 60 db. 7. input is 1 khz and 0 db. 8. measured by applying a 1 khz, 0 db signal to one channel and monitoring the level of 1 khz (fundamental) on the other channel. 9. see also section input level of chapter functional description; valid for left or right channel. analog part (v ddd =v dda =5v; t amb =25 c; f s = 48 khz) v oltage reference :v refl and v refr v o output voltage 0.475v dda 0.5v dda 0.525v dda v z n dc impedance normal mode - 750 -w z s dc impedance standby mode - 100 - k w c urrent reference :i ref v o output voltage - 0.5v dda - v i o output current r = 33 k w- 76 -m a dac reference :v dacn v i input voltage - v ssa - v v dacp v i input voltage - v dda - v b uffer operational amplifiers : bil, bol, bir and bor v offset input offset voltage -< 10 - mv r lmax maximum load resistance; (drive capability) decoupled to v ref - 10 - k w z o output impedance - 100 -w thd + n total harmonic distortion plus noise f = 0 to 20 khz -- 85 - db adc performance ; note 5 t gd group delay t = 1/f s tbf - tbf m s a sb stop band attenuation f > 0.546f s 60 -- db dr dynamic range note 6 90 -- db thd + n total harmonic distortion plus noise note 7 --- 80 db s/n signal-to-noise ratio a-weighted - tbf - db a cs channel separation note 8 - tbf - db g gain note 9 - 1.2 - 1 - 0.8 db symbol parameter conditions min. typ. max. unit
may 1994 11 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 fig.3 serial interface master mode format. mga914 sck sdo msb lsb msb lsb msb format 2 format 1 sws 1 stereo word left data right data left data right data 18 clocks 14 clocks 18 clocks 14 clocks
may 1994 12 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 fig.4 serial interface slave mode formats. sws format 2 1 stereo word left data right data mga915 1 stereo word left data right data sws format 1 sck sdo msb lsb msb lsb msb idle n clocks idle n clocks sck sdo msb lsb msb lsb msb idle n clocks idle n clocks 1 < n < 33. up to 18 significant bits are available.
may 1994 13 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 fig.5 serial interface master mode timing. mga916 msb format 1 msb format 2 valid t wh t wl t r t su t h t f t d t r t l t h t f sck sws sdo sws 2.0 v 0.8 v 2.0 v 0.8 v 2.0 v 0.8 v timing reference levels fig.6 serial interface slave mode timing. mga917 msb format 1 msb format 2 valid t wh t wl t r t su t h t f t d t r t l t h t f sck sws sdo sws 2.0 v 0.8 v 2.0 v 0.8 v 2.0 v 0.8 v timing reference levels t su
may 1994 14 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 fig.7 serial interface slave mode burst clock. mga918 t idle t idle sws sck
may 1994 15 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 application information fig.8 application circuit. handbook, full pagewidth dither mga913 left channel input w 10 k 68 pf w 330 k w 10 k 47 m f w 100 k 47 nf w 270 w 270 47 m f r w 10 k 68 pf w 620 k w 10 k 47 m f w 100 k right channel input 5 v v or v ddd ssd 47 m f 47 nf 47 m f 47 nf w 4.7 5 v 47 m f 47 nf w 33 k 22 nf 24 23 22 21 20 19 18 17 16 15 14 13 123456789101112 saa7366 system clock input to microcontroller overload detection from microcontroller power-down control 47 nf 47 m f 5 v w 4.7 to serial interface receiver circuit sfor std ovld ckin v ddd v ssd sdo sws sck test1 hpen test2 slave v dda v refl bil bol v dacp v dacn bor bir v refr i ref v ssa dither r v or v ddd ssd v or v ddd ssd (1) (1) (1) (1) (1) (1) these capacitors should preferably be surface mounted components located as close as possible to the device pins.
may 1994 16 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 package outline handbook, full pagewidth 7.6 7.4 10.65 10.00 a mbc235 - 1 0.3 0.1 2.45 2.25 1.1 0.5 0.32 0.23 1.1 1.0 0 to 8 o 2.65 2.35 detail a s 15.6 15.2 0.1 s 112 13 24 pin 1 index 0.9 0.4 (4x) 0.25 m (24x) 0.49 0.36 1.27 fig.9 plastic sol, 24-pin (so24l; sot137a). dimensions in mm.
may 1994 17 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 soldering plastic small-outline packages b ywave during placement and before soldering, the component must be fixed with a droplet of adhesive. after curing the adhesive, the component can be soldered. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 c within 6 s. typical dwell time is 4 s at 250 c. a modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. b y solder paste reflow reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. dwell times vary between 50 and 300 s according to method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 min at 45 c. r epairing soldered joints ( by hand - held soldering iron or pulse - heated solder tool ) fix the component by first soldering two, diagonally opposite, end pins. apply the heating tool to the flat part of the pin only. contact time must be limited to 10 s at up to 300 c. when using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 c. (pulse-heated soldering is not recommended for so packages.) for pulse-heated solder tool (resistance) soldering of vso packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
may 1994 18 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 notes
may 1994 19 philips semiconductors preliminary speci?cation bitstream conversion adc for digital audio systems saa7366 notes
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(01)640 000, fax. (01)640 200 italy: philips components s.r.l., viale f. testi, 327, 20162 milano, tel. (02)6752.3302, fax. (02)6752 3300. japan: philips bldg 13-37, kohnan 2 -chome, minato-ku, tokyo 108, tel. (03)3740 5028, fax. (03)3740 0580 korea: (republic of) philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02)794-5011, fax. (02)798-8022 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03)750 5214, fax. (03)757 4880 mexico: philips components, 5900 gateway east, suite 200, el paso, tx 79905, tel. 9-5(800)234-7381, fax. (708)296-8556 netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb tel. (040)783749, fax. (040)788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09)849-4160, fax. (09)849-7811 norway: box 1, manglerud 0612, oslo, tel. (022)74 8000, fax. (022)74 8341 pakistan: philips electrical industries of pakistan ltd., exchange bldg. st-2/a, block 9, kda scheme 5, clifton, karachi 75600, tel. (021)587 4641-49, fax. (021)577035/5874546. philippines: philips semiconductors philippines inc, 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (02)810 0161, fax. (02)817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)14163160/4163333, fax. (01)14163174/4163366. singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., components division, 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494. spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (02)388 7666, fax. (02)382 4382. thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (662)398-0141, fax. (662)398-3319. turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 2770, fax. (0212)269 3094 united kingdom: philips semiconductors limited, p.o. box 65, philips house, torrington place, london, wc1e 7hd, tel. (071)436 41 44, fax. (071)323 03 42 united states: integrated circuits: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 discrete semiconductors: 2001 west blue heron blvd., p.o. box 10330, riviera beach, florida 33404, tel. (800)447-3762 and (407)881-3200, fax. (407)881-3300 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 for all other countries apply to: philips semiconductors, international marketing and sales, building baf-1, p.o. box 218, 5600 md, eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-724825 scd31 ? philips electronics n.v. 1994 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 513061/1500/01/pp20 date of release: may 1994 document order number: 9397 731 80011

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